GEIASTD0005_3A Performance Testing for Aerospace and High Performance Electronic Interconnects Containing Pb-free Solder and Finishes



Issuing Committee
This document defines:
  1. 1
    A default method for those companies that require a pre-defined approach and
  2. 2
    A protocol for those companies that wish to develop their own test methods.
The default method (Section 4 of the document) is intended for use by electronic equipment manufacturers, repair facilities, or programs which, for a variety of reasons, may be unable to develop methods specific to their own products and applications. It is to be used when little or no other information is available to define, conduct, and interpret results from reliability, qualification, or other tests for electronic equipment containing Pb-free solder. The default method is intended to be conservative, i.e., it is biased toward minimizing the risk to users of AHP electronic equipment.
The protocol (Section 5 of the document) is intended for use by manufacturers or repair facilities which have the necessary resources to design and conduct reliability, qualification, or process development tests that are specific to their products, their operating conditions, and their applications. Users of the protocol will have the necessary knowledge, experience, and data to customize their own methods for designing, conducting, and interpreting results from the data. Key to developing a protocol is a firm understanding of all material properties for the Pb-free material in question as well as knowledge of package- and board-level attributes as described in Section 4.1.1. As an example, research has shown that the mechanisms for creep are very different between SnPb and Tin-Silver-Copper (SAC) solders. Understanding these mechanisms is key to determining critical test parameters such as dwell time for thermal cycling. The protocol portion of this document provides guidance on performing sufficient characterization of new materials in order to accurately define test parameters.
Use of the protocol is encouraged, since it is likely to yield more accurate results. Reference [7] provides a comprehensive overview of those technical considerations necessary in implementing a test protocol.
This document addresses the evaluation of failure mechanisms, through performance testing, expected in electronic products containing Pb-free solder. One failure mode, fatigue-failure through the solder-joint, is considered a primary failure mode in AHP electronics and can be understood in terms of physics-of-failure and life-projections. Understanding the all potential failure modes caused by Pb-free solder of AHP electronics is a critical element in defining early field-failures/reliability issues. Grouping of different failure modes may result in incorrect and/or misleading test conclusions. Failure analysis efforts should be conducted to insure that individual failure modes are identified enabling the correct application of reliability assessments and life-projection efforts.
When properly used, the methods or protocol defined in this document may be used along with the processes documented in compliance to Reference [3], to satisfy, at least in part, the reliability requirements of References [3] and [4].
This document may be used for products in all stages of the transition to Pb-free solder, including:
  • Products that have been designed and qualified with traditional SnPb electronic components, materials, and assembly processes, and are being re-qualified with use of Pb-free components
  • Products with SnPb designs transitioning to Pb-free solder; and
  • Products newly-designed with Pb-free solder.
For programs that were designed with SnPb solder, and are currently not using any Pb-free solder, the traditional methods may be used. It is important, however, for those programs to have processes in place to maintain the SnPb configuration including those outsourced or manufactured by subcontractors.
With respect to products as mentioned above, the methods presented in this document are intended to be applied at the level of assembly at which soldering occurs, i.e., circuit-card assembly level. For those users interested in COTS (commercial-off-the-shelf) testing, some guidance at box-level (e.g., power suppliers, module assemblies, etc.) is provided in Section 6.0.
IMPORTANT TO NOTE: This standard does not apply to space flight hardware. Applications that do not permit the use of Pb-free soldering for circuit board assembly, such as electronic hardware for space flight, are outside the scope of this document.
The demonstration of successful performance or acceptable reliability of hardware through a test program consistent with this Standard may be application-specific, and should not be construed as demonstrating qualification of the same hardware for a different application where Pb-free solder and finishes have been prohibited.
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SAE International Information Report, Performance Testing for Aerospace and High Performance Electronic Interconnects Containing Pb-free Solder and Finishes, SAE Standard GEIASTD0005_3A, Revised December 2012, Issued June 2008,
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Feb 12, 2018
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