Technical Challenges Running TARDEC VECTOR Software on ARM Architecture

2024-01-3508

11/15/2024

Features
Event
2024 NDIA Michigan Chapter Ground Vehicle Systems Engineering and Technology Symposium
Authors Abstract
Content
ABSTRACT

TARDEC VEA will begin integrating their Vehicular Integration for the Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance / Electronic Warfare (C4ISR/EW) Interoperability (VICTORY) Enabled Company Transformation (VECTOR) software onto three unique military vehicles in FY2015. One of the main objectives of VECTOR is to evaluate the VICTORY standard. VECTOR will use the aforementioned military vehicles as a platform for integration with the VICTORY software library (libVictory). The feasibility of expediting component integration and enhancing vehicles in theatre will be assessed; VECTOR will attempt to leverage the capabilities of libVictory in order to do so. One of the key deliverables for VECTOR is the capability to port the software applications and middleware configuration items to an embedded low-cost ARM architecture. The VECTOR team selected a unique hybrid system that includes both a single board computer and an Ethernet switch. This research paper will present the rationale for porting VECTOR software to the ARM architecture and explain the details of overcoming technical challenges therein. Due to the fact that the ARM architecture is designed for mobile applications, computing hardware resources and software availability are much more limited than common Intel-based desktop or workstation computers. Consequently, the level of technical risk is greatly increased, and the viability of executing the required full-blown, graphical desktop application is less likely. This paper will capture these shortcomings and will illustrate the difficulties of overcoming the hurdles of limited computing resources. Finally, this paper will provide some quantitative measurements of performance (resource utilization, graphical interface lag times, and update rate thresholds) as observed on the embedded ARM processor (also referred to as the target), and how certain optimizations can improve the system.

Meta TagsDetails
DOI
https://doi.org/10.4271/2024-01-3508
Pages
7
Citation
Russell, M., "Technical Challenges Running TARDEC VECTOR Software on ARM Architecture," SAE Technical Paper 2024-01-3508, 2024, https://doi.org/10.4271/2024-01-3508.
Additional Details
Publisher
Published
Nov 15
Product Code
2024-01-3508
Content Type
Technical Paper
Language
English