Semiconductor Electrostatic Discharge Damage Protection

A current problem plaguing many users of MOS discrete and integrated circuit devices is the high damage rate incurred during handling and normal assembly processes. The characteristic high impedance input gates render these devices extremely vulnerable to damage induced by electrostatic potentials commonly developed in the assembly area. Elaborate packaging schemes, handling precautions and grounding techniques are frequently employed to minimize damage rates.

The RAC, through assisting users in the determination of effective protective measures for specific situations, has compiled a library of the various techniques and philosophies which have been employed to reduce the electrostatic discharge damage rate. This paper is intended to aid design and production engineers in acquiring a fuller appreciation of the ESD problem and the precautionary measures which can be employed to control the problem. Specific topics discussed include; device properties which introduce susceptibility to ESD, sources of ESD, failure analysis methods to identify ESD damage, protective methods and materials and a review of actual application experiences.