Research on Nonlinearity of Interface ASIC for MEMS Accelerometer with Switched-Capacitor Closed-Loop Feedback

This paper investigates the nonlinearity issues in the interface ASIC system for capacitive MEMS accelerometers. First, the sources of nonlinearity in the mechanical structure of the accelerometer and the switched-capacitor interface circuit are analyzed, including the nonlinearity of mechanical displacement-to-capacitance conversion, harmonic distortion caused by parasitic capacitance, and the contradiction between range and linearity due to a low-stiffness proof mass in open-loop mode. To suppress the nonlinearity, PID control is adopted to realize closed-loop electrostatic force feedback, a loop error model is established, and a capacitor array compensation circuit is introduced to eliminate the output offset caused by parasitic capacitance. The interface ASIC is designed in a 0.18 μm BCD process, and the layout design and tape-out are completed. Pre-simulation results show a nonlinearity of 0.0124% within a 0–50 g range; post-simulation nonlinearity is 0.0657%. In actual tests, the accelerometer achieves a scale factor of 0.091 V/g over the 0–50 g range, the maximum residual of the least-squares fitting is 0.000645 V, and the nonlinearity is 0.0728%, approximately 160 ppm. This study verifies the effectiveness of closed-loop PID control and capacitance compensation in suppressing nonlinearity, providing a theoretical basis and engineering reference for the design of high-linearity MEMS accelerometers.