Performance Impacts from the seL4 Hypervisor

2024-01-3865

8/11/2020

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Abstract
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ABSTRACT

Hypervisor technologies are often presented as offering a high degree of separation at the cost of performance. Is this too expensive for embedded systems? The cost of performance has been shrinking year after year as new advancements in virtualization technologies are baked into processors. When a hypervisor couples hardware assisted virtualization with device emulation, it makes current systems portable, future proof, and extends the life of legacy systems.

seL4 is a perfect fit for the high assurance embedded hypervisor space. The open source seL4 microkernel is the first formally verified microkernel built with security and performance in mind. The mathematical proof of seL4 provides unprecedented assurance at the lowest, most critical software level.

This paper investigates the overheads associated with using seL4 as a hypervisor on ARM and x86 platforms, providing synthetic and real-world benchmarking methodology and results.

Citation: J. Millwood, R. VanVossen, L. Elliott, “Performance Impacts from the seL4 Hypervisor”, In Proceedings of the Ground Vehicle Systems Engineering and Technology Symposium (GVSETS), NDIA, Novi, MI, Aug. 13-15, 2020.

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DOI
https://doi.org/10.4271/2024-01-3865
Pages
11
Citation
Millwood, J., VanVossen, R., and Elliott, L., "Performance Impacts from the seL4 Hypervisor," SAE Technical Paper 2024-01-3865, 2020, https://doi.org/10.4271/2024-01-3865.
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Publisher
Published
8/11/2020
Product Code
2024-01-3865
Content Type
Technical Paper
Language
English