Formal Timing Analysis of Full Duplex Switched Based Ethernet Network Architectures

Ethernet could be a promising solution to satisfy the increasing bandwidth requirements of future automotive systems. While the non-deterministic timing behavior of standard Ethernet makes its application unsuitable for time critical systems, different real-time Ethernet solutions which ensure bounded communication delays exist and are also already employed in the industry. A common aspect of the existing solutions is the full duplex switched Ethernet network architecture on which they are based. This makes it possible to guarantee the existence of an upper bound of the message latency, but the determination of this bound is far from trivial in most cases. For the determination of the message latency, the behavior of all sources of traffic on the network has to be taken into account. Specifically, one must consider the maximum frame size transmitted by any device, the scheduling parameters of the frames (e.g. Class of Service (CoS) priorities), and the time distribution and rate of frames. In this paper, we present how the concepts used in compositional system level performance analysis can be adapted to analyze full duplex switched based network architectures. We also demonstrate the feasibility of the formal approach by analyzing a system based upon a prominent real time Ethernet solution, namely AFDX, and compare the obtained results with results obtained by simulation.