CPU Model-based Hardware/Software Co-design for Real-Time Embedded Control Systems



SAE World Congress & Exhibition
Authors Abstract
This paper proposes a new development method for highly reliable real-time embedded control systems using a CPU model-based hardware/software co-simulation. We take an approach that allows the full simulation of the virtual mechanical control system including CPU and object code level software. In this paper, Renesas SH-2A microcontroller model was developed on CoMET™ platform from VaST Systems Technology. A ETC (Electronic Throttle Control) system and engine control system were chosen to prove this concept. The ETB (Electronic Throttle Body) model on Saber® simulator from Synopsys® or engine model on MATLAB®/Simulink® simulator from MathWorks can be simulated with the SH-2A model. To help the system design, debug and evaluation, we developed an integrated behavior analyzer, which can display CPU behavior graphically during the simulation without affecting the simulation result, such as task level CPU load, interrupt statistics, software variable transition chart, and so on. The software has not been modified for this virtual system analysis. This analyzer provides useful information what happens in the system and it should be system HW/SW debugging tools for hard real-time control system. The SH-2A chip was under development during this project, nevertheless we could complete the OSEK OS development, control software design and verification. We already confirmed that this software could run on an actual ETC hardware system without modification after working sample chip released.
Meta TagsDetails
Ishikawa, M., McCune, D., Saikalis, G., and Oho, S., "CPU Model-based Hardware/Software Co-design for Real-Time Embedded Control Systems," SAE Technical Paper 2007-01-0776, 2007, https://doi.org/10.4271/2007-01-0776.
Additional Details
Apr 16, 2007
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Content Type
Technical Paper