Challenges and Mitigations for Data Remanance in FPGA Based Systems

2024-01-4112

08/10/2023

Features
Event
2024 NDIA Michigan Chapter Ground Vehicle Systems Engineering and Technology Symposium
Authors Abstract
Content
FPGA based electronic systems have the potential to support zeroization and sanitization of sensitive information without resorting to kinetic destruction. However, careful consideration needs to be given to the data remanence effects of both the FPGA and the attached storage media that form a complete system. SRAM, DRAM, and different forms of flash memory all have distinct data remanence characteristics that must be accounted for in the design of zeroization solutions. In this paper, we survey these characteristics across typical FPGA system media types and present a framework to enable the rapid integration of complete zeroization and sanitization capabilities in FPGA systems.
Meta TagsDetails
DOI
https://doi.org/10.4271/2024-01-4112
Pages
13
Citation
Paar, K., and Harper, S., "Challenges and Mitigations for Data Remanance in FPGA Based Systems," SAE Technical Paper 2024-01-4112, 2023, https://doi.org/10.4271/2024-01-4112.
Additional Details
Publisher
Published
Aug 10, 2023
Product Code
2024-01-4112
Content Type
Technical Paper
Language
English