Architecture and Operation of the HIP7010 J1850 Byte-Level Interface Circuit
950035
02/01/1995
- Event
- Content
- As a cost effective solution to making microcontroller based systems “J1850[1] aware”, a peripheral device (the HIP7010) was developed to extend the capabilities of standard microcontrollers. From the perspective of the Host, the peripheral device handles J1850 messages as a series of bytes (similar in concept to a universal asynchronous receiver/transmitter [UART]).The architecture of the HIP7010 is discussed. The design of the J1850 interface, state machine, status/control blocks, cyclical redundancy check (CRC) hardware, host interface, and fail-safe features are detailed. Illustrations are provided of: Host/HIP7010 interfacing; message transmission and reception; error handling; and In-Frame Response (IFR) generation.
- Pages
- 21
- Citation
- Sferrazza, P., Halter, R., and Stark, J., "Architecture and Operation of the HIP7010 J1850 Byte-Level Interface Circuit," SAE Technical Paper 950035, 1995, https://doi.org/10.4271/950035.