An Architecture for Electronic Throttle Control Systems

This paper presents an architecture for monitoring and controlling an electronic throttle control system. The architecture contains two processors, the MAIN and the MCP. The MAIN is responsible for calculating the desired throttle position and the MCP for positioning the throttle using feedback control. The two processors measure all pedal and throttle sensors redundantly and continuously monitor the state-of-health of the other processor. Depending on the fault(s) detected, actuator default position, limited throttle authority, forced idle, Bowden cable mode or engine shutdown remedial action may be taken.