A PC and FPGA Hybrid Approach to Hardware-in-the-Loop Simulation

ECU designers are seeking more flexibility from HIL test systems. Often their needs are met by the development of custom hardware, either internally or by HIL test system vendors. Many systems also rely heavily on the use of multiple expensive microprocessors to achieve the required timing and synchronization performance. This paper discusses an alternative based on PC technology and reconfigurable I/O hardware. The HIL test system designer uses a graphical programming interface to reconfigure not only the real-time software portion of the system, but also the FPGA-based I/O hardware. This increases flexibility and lowers cost by providing capabilities such as generating simulated outputs synchronized to crank angle and implementing multiple serial communication protocols.