A Fault-Tolerant Processor Core Architecture for Safety-Critical Automotive Applications

2005-01-0322

04/11/2005

Event
SAE 2005 World Congress & Exhibition
Authors Abstract
Content
The introduction of drive-by-wire systems into modern vehicles has generated new challenges for the designers of embedded systems. These systems, based primarily on microcontrollers, need to achieve very high levels of reliability and availability, but also have to satisfy the strict cost and packaging constraints of the automotive industry. Advances in VLSI technology have allowed the development of single-chip systems, but have also increased the rate of intermittent and transient faults that come as a result of the continuous shrinkage of the CMOS process feature size. This paper presents a low-cost, fault-tolerant system-on-chip architecture suitable for drive-by-wire and other safety-related applications, based on a triple-modular-redundancy configuration at the processor execution pipeline level.
Meta TagsDetails
DOI
https://doi.org/10.4271/2005-01-0322
Pages
8
Citation
Touloupis, E., Flint, J., Chouliaras, V., and Ward, D., "A Fault-Tolerant Processor Core Architecture for Safety-Critical Automotive Applications," SAE Technical Paper 2005-01-0322, 2005, https://doi.org/10.4271/2005-01-0322.
Additional Details
Publisher
Published
Apr 11, 2005
Product Code
2005-01-0322
Content Type
Technical Paper
Language
English