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An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization
ISSN: 1946-3855, e-ISSN: 1946-3901
Published October 22, 2012 by SAE International in United States
Citation: Trentin, D., Savaria, Y., Zhu, G., and Thibeault, C., "An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization," SAE Int. J. Aerosp. 5(1):181-188, 2012, https://doi.org/10.4271/2012-01-2123.
Avionic Full-Duplex Switched Ethernet (AFDX) is one of the most promising solutions developed in recent years for implementing high-bandwidth Avionic Data Networks (ADNs) that can support the increasingly high information flow required by modern avionic systems. Although AFDX commercial products are available, developing custom implementations using generic software and hardware, without depending on third-party products, allows identifying practical challenges and constraints, prototyping and characterizing new architectures, testing new algorithms, as well as performing validation and verification in the early stage of development. In this paper, we show how an AFDX switch fabric hardware core can be designed and implemented on an FPGA to facilitate the prototyping of a generic ADN in an early development stage. This implementation is compatible with a generic platform that provides connections with a PC offering multiple physical ports and supports the generation of custom traffics for system validation and characterization. More specifically, the developed switch fabric component is a soft core configurable at synthesis time to support from 2 to 24 ports, resulting in a core size that needs from 10k to 65k LUTs on a Spartan-6 FPGA. A 3-port switch fabric has been integrated on a XC6SLX45T FPGA, which will be used to validate the system behaviour in a real network. The Scheduler behaviour and the resulting average latency introduced do not depend on the switch size, but rather on the incoming traffic load. It is also demonstrated how a maximum sized switch fabric (24 ports) can guarantee that no input congestion occurs for traffic up to 25Mbit/s per port. In order to reduce high priority frames latency, low priority frames are stored in a separate buffer, thus making critical traffic processing mostly insensitive to their presence. The queues allocated to non-critical traffic can also be used to store critical frames whenever the main buffer fails due to hardware problems or when it is full, thus reducing the possibility of frame loss.