Streamlining circuit design

Alcatel conquers the next frontier of satellite design with algorithmic C synthesis.

Within the Toulouse division of Alcatel Space, which supplies geostationary, low-Earth-orbit, and specific-mission satellites, a digital design team comprising 12 engineers is combating shrinking time-to-market (TTM) goals by decreasing the amount of time needed to create ASICs (application-specific integrated circuits).

Time constraints limited the exploration of the multitude of register transfer level (RTL) micro-architectural options available for its next-generation algorithms. Meeting aggressive TTM schedules was further complicated because early in the design process algorithms are typically modeled at a higher level of abstraction, usually in ANSI C/C++ programming language. These high-level C++ models are then used to develop a specification that hardware designers employ to create a RTL description of the algorithm. This discontinuity between the C++ model and the RTL description is a bottleneck in the design process, and the manual design translation is a potential entry point for errors.