SEU-Tolerant Flip-Flops

Several improvements in the designs of flip-flop circuits that are parts of logic circuits have been proposed to reduce the incidence of logic errors associated with single- event upsets (SEUs) [bit flips caused by incident energetic ionizing particles]. Traditionally, radiation-hardened integrated circuits have been manufactured on special process lines, with emphasis, variously, on immunity to latchups and SEUs for outer-space applications or on total-dose hardness for military applications. The present improvements are intended to confer latchup and SEU immunity of a degree and type suitable for outer-space applications, but unlike in the traditional approach, the improved designs could be implemented on ordinary commercial complementary metal oxide semiconductor (CMOS) process lines.