Parallel-Processing High-Rate Digital Demodulator ASIC
TBMG-3040
03/01/2002
- Content
An all-digital demodulator has been developed for receiving radio signals with multigigahertz carrier frequencies phase-modulated with digital data signals at bit rates of hundreds of millions of bits per second. The phase modulation could be either binary phase-shift keying (BPSK) or quadrature phase-shift keying (QPSK), including QPSK employing bandwidth efficient pulse-shaping methods. The demodulator has been implemented in complementary metal oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) configured to utilize algorithms that process signal data in multiple parallel streams.
- Citation
- "Parallel-Processing High-Rate Digital Demodulator ASIC," Mobility Engineering, March 1, 2002.