Parallel-Processing Equalizers for Multi-Gbps Communications

Architectures have been proposed for the design of frequency-domain least-mean-square complex equalizers that would be integral parts of parallel-processing digital receivers of multigigahertz radio signals and other quadrature - phase - shift - keying (QPSK) or 16 - quadrature - amplitude - modulation (16-QAM) of data signals at rates of multiple gigabits per second. "Equalizers" as used here denotes receiver subsystems that compensate for distortions in the phase and frequency responses of the broad-band radio-frequency channels typically used to convey such signals. The proposed architectures are suitable for realization in very-large-scale integrated (VLSI) circuitry and, in particular, complementary metal oxide semiconductor (CMOS) application-specific integrated circuits (ASICs) operating at frequencies lower than modulation symbol rates.