Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI
TBMG-14230
08/01/2012
- Content
For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction.
- Citation
- "Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI," Mobility Engineering, August 1, 2012.