Mixed Linear/Square-Root Encoded Single-Slope Ramp Provides Low-Noise ADC With High Linearity for Focal Plane Arrays

Single-slope analog-to-digital converters (ADCs) are particularly useful for on-chip digitization in focal plane arrays (FPAs) because of their inherent monotonicity, relative simplicity, and efficiency for column-parallel applications, but they are comparatively slow. Square-root encoding can allow the number of code values to be reduced without loss of signal- to-noise ratio (SNR) by keeping the quantization noise just below the signal shot noise. This encoding can be implemented directly by using a quadratic ramp. The reduction in the number of code values can substantially increase the quantization speed. However, in an FPA, the fixed pattern noise (FPN) limits the use of small quantization steps at low signal levels. If the zero-point is adjusted so that the lowest column is onscale, the other columns, including those at the center of the distribution, will be pushed up the ramp where the quantization noise is higher.