Larger-Area Integrated Electrical Metallization Dielectric Structures with Stress-Managed Unit Cells for Extreme- Environment Semiconductor Electronics Chips

The use of patterned multiple layers of thin films of metal and dielectric to form integrated circuit interconnections of transistors and/or form on-chip circuit capacitors is well known to those skilled in the art of semiconductor microelectronic fabrication. Because differing layers of thin film materials have different physical and thermal expansion properties, it is also well known that stress is inherently present in these multilayer film structures on a microelectronic chip. The amount of stress changes with temperature and as a function of lateral feature size/area across the chip. When stress anywhere within a patterned metal film feature becomes critically large (i.e., the “yield stress” is exceeded), the metal film can physically crack, buckle, or delaminate from other layers, which usually damages/fails the intended electrical operation of the microelectronic circuit.