An Investigation into Multi-Core Architectures to Improve a Processing Performance of the Unified Chassis Control Algorithms

Event
SAE 2010 World Congress & Exhibition
Authors Abstract
Content
This paper describes an investigation into multi-core processing architecture for implementation of a Unified Chassis Control (UCC) algorithm. The multi-core architecture is suggested to reduce the operating load and maximization of the reliability to improve of the UCC system performance. For the purpose of this study, the proposed multi-core architecture supports distributed control with analytical and physical redundancy capabilities. In this paper, the UCC algorithm embedded in electronic control unit (ECU) is comprised of three parts; a supervisor, a main controller, and fault detection/ isolation/ tolerance control (FDI/FTC). An ECU is configured by three processors, and a control area network (CAN) is also implemented for hardware-in-the-loop (HILS) evaluation. Two types of multi-core architectures such as distributed processing, and triple voting are implemented to investigate the performance and reliability. A vehicle simulator and brake HILS are used to evaluate the proposed multi-core architectures. From the test results, it is shown that all of the proposed multi-core systems have better performance and improved reliability compared with the single-core system.
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DOI
https://doi.org/10.4271/2010-01-0662
Pages
10
Citation
Seo, K., Chung, T., Heo, H., Yi, K. et al., "An Investigation into Multi-Core Architectures to Improve a Processing Performance of the Unified Chassis Control Algorithms," Passenger Cars - Electronic and Electrical Systems 3(1):53-62, 2010, https://doi.org/10.4271/2010-01-0662.
Additional Details
Publisher
Published
Apr 12, 2010
Product Code
2010-01-0662
Content Type
Journal Article
Language
English