Magazine Article

Implementing a Digital Phasemeter in an FPGA

TBMG-3187

09/01/2008

Abstract
Content

Firmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally-equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses (see figure), the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains.

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Citation
"Implementing a Digital Phasemeter in an FPGA," Mobility Engineering, September 1, 2008.
Additional Details
Publisher
Published
Sep 1, 2008
Product Code
TBMG-3187
Content Type
Magazine Article
Language
English