As software (SW) becomes more and more an important aspect of embedded system development, project schedules are requiring the earlier development of software simultaneously with hardware (HW). In addition, verification has increasingly challenged the design of complex mixed-signal SoC products. This is exacerbated for automotive safety critical SoC products with a high number of analogue interfaces (sensors and actuators) to the physical components such as an airbag SoC chipset. Generally, it is widely accepted that verification accounts for around 70% of the total SoC development. Since integration of HW and SW is the most crucial step in embedded system development, the sooner it is done, the sooner verification can begin. As such, any approaches which could allow verification and integration of HW/SW to be deployed earlier in the development process and help to decrease verification effort, (e.g.: accelerate verification runs) are of extreme interest.
In the described context, this paper addresses not only the design and verification challenges of such embedded systems but also proposes a new development, verification and validation workflow using an FPGA-based SoC Emulation System with synthesizable analogue functional stubs and a risk minimizing analogue test chip, which emulates and partially implements respective mixed-signal behavior of the ASIC SoC hardware. The workflow can also be called FPGA-in-the-Loop (FiL) and it is proven to help multi-disciplinary development teams to vastly improve the quality of HW/SW co-design at system level with as little time and effort as possible.
