Fabrication of Arrays of Large Step-Free Regions on Si(100)

When a silicon wafer is cut from an ingot, it is essentially impossible to align the cut perfectly with the crystal structure. Therefore the surface contour of the wafer will be a flat plane on which terraces consisting of additional atomic layers will be scattered. An atomic step will be found on the surface where each additional layer is encountered. At elevated temperatures, these atomic steps will migrate, but they cannot be eliminated. At the current level of device technology, the effects of steps on the wafer surface can be largely ignored. In future generations of integrated circuits, however, the sizes of these steps will become comparable to some device feature sizes and will affect circuit performance and yields.