Error-Detecting Counters for FPGA and ASIC State Machines

Error-detecting counters have been proposed as parts of fault-tolerant finite state machines that could be implemented in field-programmable gate arrays (FPGAs) and application-specific integrated circuits that perform sequential logic functions. The use of error-detecting counters would complement the fault-tolerant coding schemes described in “Fault-Tolerant Coding for State Machines” (NPO-41050), in this issue on page 55. Counters are often used in state machines in cases in which it is necessary to represent large numbers of states and/or to count clock cycles between certain states. To ensure reliability, it is necessary to ensure that the counters are as free of faults as are the other parts of the state machines.