Asymmetric Core Computing for High-Performance Applications

High-performance computing (HPC) users have traditionally relied upon two things to supply them with processing power: speed of the central processing units (CPUs) and the scalability of the system. There are problems with this approach. Physical limitations are curtailing clock speed increases in general-purpose CPUs, the von Neumann load-execute-store approach does not map well to every computational problem, and systems of thousands of processors might be very inefficient, depending upon processor interconnection limitations.Blending asymmetric computing resources makes sense for addressing the needs relating to the U.S. Army HPC perspective. Several versatile, commodity-based options are coming online that now include throughput architectures such as graphics processing units (GPUs), reconfigurable systems built on field-programmable gate arrays (FPGAs), multi- and many-core x86-based systems, and heterogeneous systems such as the Cell processor (incorporating a standard CPU and vector processing unit). These options allow for smaller footprint systems with tremendous speed-ups compared to traditionally large clusters of von Neumann general-purpose CPUs.