Assembly of Nanowire-Based Computing Systems

A program to develop ultra-dense integrated digital data-processing systems and circuits based on nanowires involves utilization of hybrid top-down and bottom-up assembly techniques to implement designs representative of a highly reliable defect- and fault-tolerant architecture. This program has included fabrication and assembly of molecular- scale logic blocks based on arrays of overlapping semiconducting nanowires, using novel wafer-scale assembly techniques. On the basis of breakthrough addressing techniques, these logic blocks have been connected to ultradense memory blocks and to external complementary oxide/semiconductor (CMOS)-process lithographic interfaces for testing. One of the main underlying ideas is to construct highly reliable components out of high-defect-density logic and memory elements, using recently developed sublithographic-scale programmable- logic-array architectures that incorporate novel reliable-circuit concepts and higher-level redundancy mechanisms. Using state-of-the-art modeling techniques and computational simulations, test designs have been optimized, various defect-tolerance approaches have been developed, and development and optimization of larger systems are continuing.