ASIC for Viterbi Decoding With 2 ≤ K ≤ 15 and 1/2 ≥ r ≥ 1/6

An application-specific integrated circuit (ASIC) serves as a building block for a digital system that effects maximum-likelihood decoding of a Viterbi code (a binary convolutional error-correcting code) with a constraint length (K) in the range of 2 through 15 and a rate (r) in the range of 1/2 through 1/6. This ASIC is based on the same architecture as that of two older prototype K = 15, r = 1/6 Viterbi decoders, the first of which was reported in literature in 1988. These prototypes have functioned successfully in experiments, and their capabilities exceed those of state-of-the-art (K up to 7 andr at 1/2) commercial decoders as of the time of reporting the information for this article, but they have not been put into commercial production, partly because their complexities have given rise to reliability problems. Moreover, these prototypes have been limited to decoding speeds ≤ 750 kb/s.