Published November 9, 2016 by SAE International in United States
The Time-Triggered Ethernet (SAE AS6802) standard defines a fault-tolerant synchronization strategy for building and maintaining synchronized time in a distributed system of end systems and switches (we use the term end system for “data terminal equipment” (DTE) as specified in IEEE 802.3), which can be used to support communication among these components for traffic, which may have different levels of time criticality. In particular, the standard defines algorithms for clock synchronization, clique detection, startup, and restart. These algorithms have been designed to allow scalable fault-tolerance and provide self-stabilization mechanisms.
Time-Triggered Ethernet supports the design of communication systems with mixed time criticality in which several applications of mixed time criticality share a single physical network. In particular, an Ethernet network can be used to transfer frames in a time-triggered mode (synchronous communication) and non-time-triggered modes (asynchronous communication as for example Ethernet frames transmitted according to the best-effort strategy). The Time-Triggered Ethernet synchronization strategy inherently compensates for latency and jitter resulting from this integration and ensures high-quality synchronization despite increased network latency and jitter. Synchronized time provides the foundation for partitioning and isolation of critical applications from the less critical or non-critical ones.
End systems exchange application data with each other by transmitting standard Ethernet frames. The points in time when end systems dispatch these frames can be coupled to the synchronized time. The transfer of these frames is then called time-triggered transfer, because the trigger for frame dispatch is derived from time. Time-Triggered Ethernet formally defines the relationship between the synchronized time and the time-triggered transfer.
Time-Triggered Ethernet covers only the network aspects for mixed time-criticality systems1. Time-Triggered Ethernet does not address how to integrate mixed time-criticality applications within a single node. Hence, partitioning strategies for shared resources other than the network, e.g., memory partitioning, are not discussed in Time-Triggered Ethernet. Furthermore, the fault-tolerance strategies discussed in AS6802 also address only the networking aspects. Time-Triggered Ethernet does not specify or recommend any complete system architecture for highly reliable systems.
AS6802 has been reaffirmed to comply with the SAE five-year review policy.
Data Sets - Support Documents
|[Unnamed Dataset 1]|
|TABLE 1||COMPRESSION OF COLDSTART FRAMES|
|TABLE 2||PCF PAYLOAD|
|TABLE X.1||SM_INTEGRATE STATE TRANSITION SUMMARY|
|TABLE X.2||SM_UNSYNC STATE TRANSITION SUMMARY|
|TABLE X.3||SM_FLOOD STATE TRANSITION SUMMARY|
|TABLE X.4||SM_WAIT_4_CYCLE_START_CS STATE TRANSITION SUMMARY|
|TABLE X.5||SM_TENTATIVE_SYNC STATE TRANSITION SUMMARY|
|TABLE X.6||SM_SYNC STATE TRANSITION SUMMARY|
|TABLE X.7||SM_STABLE STATE TRANSITION SUMMARY|
|TABLE X.8||SM_WAIT_4_CYCLE_START STATE TRANSITION SUMMARY|
|TABLE X.10||SC_SYNC STATE TRANSITION SUMMARY|
|TABLE X.11||SC_STABLE STATE TRANSITION SUMMARY|
|TABLE X.12||CM_INTEGRATE STATE TRANSITION SUMMARY|
|TABLE X.13||CM_WAIT_4_CYCLE_START STATE TRANSITION SUMMARY|
|TABLE X.14||CM_UNSYNC STATE TRANSITION SUMMARY|
|TABLE X.15||CM_TENTATIVE_SYNC STATE TRANSITION SUMMARY|
|TABLE X.16||CM_SYNC STATE TRANSITION SUMMARY|
|TABLE X.17||CM_STABLE STATE TRANSITION SUMMARY|
|TABLE X.18||CM_INTEGRATE STATE TRANSITION SUMMARY|
|TABLE X.19||CM_UNSYNC STATE TRANSITION SUMMARY|
|TABLE X.21||CM_WAIT_4_IN STATE TRANSITION SUMMARY|
|TABLE X.22||CM_SYNC STATE TRANSITION SUMMARY|
|TABLE X.23||CM_STABLE STATE TRANSITION SUMMARY|
|TABLE 3||SM THRESHOLD ASSIGNMENTS FOR THE TWO FAULT-TOLERANT HIGH-INTEGRITY SM CONFIGURATION|
|TABLE 4||SM THRESHOLD ASSIGNMENTS FOR THE FAULT-TOLERANT STANDARD-INTEGRITY SM CONFIGURATION|
|TABLE 5||CM THRESHOLD ASSIGNMENTS FOR THE TWO FAULT-TOLERANT HIGH-INTEGRITY SM/CM CONFIGURATION|
|TABLE 6||CM THRESHOLD ASSIGNMENTS FOR THE TWO FAULT-TOLERANT HIGH-INTEGRITY SM/CM CONFIGURATION|
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