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Architecture and Operation of the HIP7030A2 8-Bit J1850 Microcontroller
ISSN: 0148-7191, e-ISSN: 2688-3627
Published February 01, 1995 by SAE International in United States
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A 6805 based microcontroller (HIP7030A2) was developed with integrated J1850 hardware. Trade-offs were made between hardware and software in terms of cost, speed, memory requirements, and processor overhead. The microcontroller has been used to construct J1850 compliant, single-byte and three-byte header, variable pulse width (VPW) nodes. Algorithms for symbol processing, cyclical redundancy check (CRC) generation/verification, and message filtering were developed which validate the suitability of the HIP7030A2 for stand-alone and dual-processor nodes.
Firmware was developed which transforms the HIP7030A2 into a J1850 message coprocessor for single-byte header, VPW messages. Known as the Programmable Communications Interface (PCI) it serves as a slave device to host processors dramatically simplifying the task of J1850 enabling a module.
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CitationHarmon, J., Randel, R., and Sferrazza, P., "Architecture and Operation of the HIP7030A2 8-Bit J1850 Microcontroller," SAE Technical Paper 950034, 1995, https://doi.org/10.4271/950034.
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