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A Lightweight Spatio-Temporally Partitioned Multicore Architecture for Concurrent Execution of Safety Critical Workloads
ISSN: 0148-7191, e-ISSN: 2688-3627
Published September 20, 2016 by SAE International in United States
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Modern aircraft systems employ numerous processors to achieve system functionality. In particular, engine controls and power distribution subsystems rely heavily on software to provide safety-critical functionality, and are expected to move toward multicore architectures. The computing hardware-layer of avionic systems must be able to execute many concurrent workloads under tight deterministic execution guarantees to meet the safety standards. Single-chip multicores are attractive for safety-critical embedded systems due to their lightweight form factor. However, multicores aggressively share hardware resources, leading to interference that in turn creates non-deterministic execution for multiple concurrent workloads. We propose an approach to remove on-chip interference via a set of methods to spatio-temporally partition shared multicore resources. Our proposed partitioning scheme is bounded within the worst case execution, and ensures efficient performance and deterministic execution.
CitationShi, Q., Lakshminarashimhan, K., Noll, C., Scholte, E. et al., "A Lightweight Spatio-Temporally Partitioned Multicore Architecture for Concurrent Execution of Safety Critical Workloads," SAE Technical Paper 2016-01-2067, 2016, https://doi.org/10.4271/2016-01-2067.
- Nuzzo, Pierluigi, et al. ”A contract-based methodology for aircraft electric power system design.” Access, IEEE 2 (2014): 1-25.
- Shi Qingchuan; Hijaz, F.; Khan, O., ”Towards efficient dynamic data placement in NoC-based multicores,” in Computer Design (ICCD), IEEE 31st International Conference on , vol., no., pp.369-376, 6-9 Oct. 2013.
- Miller, J.E.; Kasture, H.; Kurian, G.; Gruenwald, C.; Beckmann, N.; Celio, C.; Eastep, J.; Agarwal, A., ”Graphite: A distributed parallel simulator for multicores,” in High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on, vol., no., pp.1-12, 9-14 Jan. 2010.
- Krishna and Poovendran. ”Aviation cyberphysical systems: foundations for future aircraft and air transport.” Proceedings of the IEEE 101.8 (2013): 1834-1855.
- Certification Authorities Software Team(CAST), CAST-32 Multicore Processors, May 2014(Rev 0) http://www.faa.gov/aircraft/air_cert/design_approvals/air_software/cast/cast_papers/media/cast-32.pdf
- Wilhelm, Reinhard, et al. ”The worst-case execution-time problemoverview of methods and survey of tools.” ACM Transactions on Embedded Computing Systems (TECS) 7.3 (2008): 36.
- Nowotsch, Jan, and Paulitsch Michael. ”Leveraging multi-core computing architectures in avionics.” Dependable Computing Conference (EDCC), 2012 Ninth European. IEEE, 2012.
- Bui, Bach Duy, et al. ”Impact of cache partitioning on multi-tasking real time embedded systems.” Embedded and Real-Time Computing Systems and Applications, 2008. RTCSA’08. 14th IEEE International Conference on. IEEE, 2008.
- Slijepcevic, Mladen, et al. ”Time-analysable non-partitioned shared caches for real-time multicore systems.” Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE. IEEE, 2014.
- Hardavellas, Nikos, et al. ”Reactive NUCA: near-optimal block placement and replication in distributed caches.” ACM SIGARCH Computer Architecture News. Vol. 37. No. 3. ACM, 2009.
- Wang Yao, Ferraiuolo Andrew, and Suh G. Edward,”Timing Channel Protection for Memory Controllers.” 20th IEEE International Symposium on High Performance Computer Architecture(HPCA), February 2014.
- Qureshi Moinuddin. K, Patt Yale N.. ”Utility Based Cache Partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches.” In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture(MICRO), 2006
- Kasture Harshad and Sanchez Daniel. ”Ubik:Efficient Cache-Sharing with strict QoS for Latency-Critical Workloads.” Proceedings of the seventeenth edition of ASPLOS on Architectural support for programming languages and operating systems,(ASPLOS),2014
- Ahmad Masab, Hijaz Farrukh, Shi Qingchuan, and Khan Omer. ”CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores.” In Workload Characterization (IISWC), 2015 IEEE International Symposium on, 2015
- Muralidhara Sai Prashanth, Subramanian Lavanya, Mutlu Onur, Kandemir Mahmut, and Moscibroda Thomas. ”Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning.” Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011
- Woo S. C., Ohara M., Torrie E., Singh J. P., and Gupta A.. ”The SPLASH-2 Programs: Characterization and Methodological Considerations.” In Intl Symposium on Computer Architecture, 1995.
- Ungerer T. et al., ”Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability.” in IEEE Micro, vol. 30, no. 5, pp. 66-75, Sept.-Oct. 2010.
- Embedded Multi-Core systems for Mixed Criticality applications in dynamic and changeable real-time environments, http://www.artemis-emc2.eu
- Burns A., Harbin J. and Indrusiak L. S., ”A Wormhole NoC Protocol for Mixed Criticality Systems.” Real-Time Systems Symposium (RTSS), 2014 IEEE, Rome, 2014, pp. 184-195.
- Paolieri M., Quinones E., Cazorla F. J., Bernat G., and Valero M., Hardware support for WCET analysis of hard real-time multicore systems. 36th Int. Symposium on Computer Architecture, June 2009.
- Kelter T., Falk H., Marwedel P., Chattopadhyay S., and Roychoudhury A., Bus-aware multicore WCET analysis through TDMA offset bounds. in 23rd Euromicro Conf. on Real-Time Systems (ECRTS), July 2011, pp. 312.
- QorIQ T2080 and T2081 communication processors, http://cache.nxp.com/files/32bit/doc/fact_sheet/T2080FS.pdf