Title |
Description |
Download |
TABLE 1 |
Bus Configuration Types |
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Unnamed Dataset 2 |
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TABLE 2 |
Pi-Bus Signal line Requirements By Type, Class and Mode |
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Unnamed Dataset 4 |
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Unnamed Dataset 5 |
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TABLE 3 |
Pi-Bus Cycle Types and Valid Symbols |
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Unnamed Dataset 7 |
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TABLE 4 |
Interpretation of Cycle Type Symbols |
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TABLE 5 |
Acknowledge Line Set Valid Symbols |
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TABLE 6 |
Pi-Bus Signal Pairing |
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TABLE 7 |
Signal Partitioning |
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TABLE 8 |
Pi-Bus Communications Sequences |
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TABLE 9 |
Pi-Bus Protocol States |
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TABLE 10 |
Generic Pi-Bus Message Sequence |
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TABLE 11 |
Mixed Mode Data Format Matrix |
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TABLE 12 |
Message Type Codes |
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TABLE 13 |
AT (Access Type) Code Assignments |
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TABLE 14 |
Multiple Slave Acknowledge Symbol Formats (Four Words) |
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TABLE 15 |
Multiple Slave Acknowledge Symbols (Four Words) Data Check Line Formats (Used only for Class EC) |
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TABLE 16 |
Bus State Definitions |
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TABLE 17 |
Vie Sequence |
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TABLE 18 |
Module Vie Code Format - Data lines |
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TABLE 19 |
Module Vie Code Format - Data Check Lines |
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TABLE 20 |
Parameter Write Sequence - Type 16 ED Single Slave |
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TABLE 21 |
Parameter Write Sequence - Type 16 ED Multiple Slave |
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TABLE 22 |
Parameter Write Sequence - Type 32 EC Single Slave |
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TABLE 23 |
Parameter Write Sequence - Type 32 EC Multiple Slave |
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TABLE 24 |
Block Message - SH Sequence - Type 16 ED Single Slave |
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TABLE 25A |
Bus State HO to Bus State HA4 |
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TABLE 25B |
Bus State D0 to Bus State DA4 |
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TABLE 26 |
Block Message - SH Sequence - Type 32 EC Single Slave |
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TABLE 27A |
Bus State H0 to Bus State HA4 |
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TABLE 27B |
Bus State D0 to Bus State DA4 |
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TABLE 28A |
Bus State H0 to Bus State HA0 |
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TABLE 28B |
Bus State D0 to Bus State DA0 |
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TABLE 29A |
Bus State H0 to Bus State HA2 |
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TABLE 29B |
Bus State HA3 to Bus State DA4 |
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TABLE 30A |
Bus State H0 to Bus State HA0 |
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TABLE 30B |
Bus State D0 to Bus State DA0 |
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TABLE 31A |
Bus State H0 to Bus State HA4 |
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TABLE 31B |
Bus State D0 to Bus State DA4 |
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TABLE 32 |
Bus Interface Message Sequence - Type 16 ED and Type 32 EC Single Slave |
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TABLE 33A |
Bus State H0 to Bus State HA4 |
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TABLE 33B |
Bus State D0 to Bus State DA4 |
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TABLE 34 |
Datagram Message (Non-Acknowledged) - SH Sequence Type 16 ED Multiple Slave |
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TABLE 35 |
Datagram Message (Non-Acknowledged) - SH Sequence Type 32 EC Multiple Slave |
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TABLE 36 |
Acknowledged Datagram Message - SH Sequence Type 16 ED Multiple Slave |
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TABLE 37 |
Acknowledged Datagram Message - SH Sequence Type 32 EC Multiple Slave |
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TABLE 38 |
Datagram Message (Non-Acknowledged) - EH Sequence Type 16 ED Multiple Slave |
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TABLE 39 |
Datagram Message (Non-Acknowledged) - EH Sequence |
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TABLE 40A |
Bus State H0 to Bus State Dn |
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TABLE 40B |
Bus State Dz to Bus State DA0 |
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TABLE 41A |
Bus State H0 to Bus State Dn |
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TABLE 41B |
Bus State Dz to Bus State DA0 |
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TABLE 42 |
Suspend - Short Data Sequence - Type 16 ED Single Slave |
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TABLE 43 |
Suspend - Short Data Sequence - Type 32 EC Single Slave |
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TABLE 44 |
Suspend - Extended Data Sequence - Type 16 ED Single Slave |
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TABLE 45 |
Suspend - Extended Data Sequence - Type 32 EC Single Slave |
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TABLE 46 |
Suspend - Type 16 ED Block Message Multiple Slave |
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TABLE 47 |
Suspend - Type 32 EC Block Message Multiple Slave |
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TABLE 48 |
Suspend - Type 16 ED Non-Acknowledged Datagram Multiple Slave |
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TABLE 49 |
Suspend - Type 32 EC Non-Acknowledge Datagram Multiple Slave |
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TABLE 50 |
Suspend - Type 16 ED Acknowledged Datagram Multiple Slave |
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TABLE 51 |
Suspend - Type 32 EC Acknowledged Datagram Multiple Slave |
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TABLE 52 |
Abort Sequence |
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TABLE 53 |
Data link Address Space |
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TABLE 54 |
Interpretation for Uncorrectable Invalid Symbol |
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TABLE 55 |
Slave Response to Cycle Type Sequence Deviations |
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TABLE 56 |
Cycle Type Deviation Response Definitions |
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TABLE 57 |
Sequence Error Response |
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TABLE 58 |
Semantic Errors |
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TABLE 59 |
Acknowledge Semantic Error |
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Error Table 1 |
Message Type Format Errors (Slave Mode Operation) |
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Error Table 2 |
Block Message Format and Device Errors (Slave Mode Operation) |
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Error Table 2A |
Block Message Header Format and Device Errors (Slave Mode Operation for Label Block Messages) |
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Error Table 3 |
Acknowledged Datagram Message (AT = 4-7) Format and Device Error (Slave Mode Operation) |
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Error Table 3A |
Non-Acknowledged Datagram Message (AT = 0-3) Format and Device Error (Slave Mode Operation) |
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Error Table 4 |
Parameter Write Message Format Errors (Slave Mode Operation) |
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Error Table 5 |
Bus Interface Message Format Errors (Slave Mode Operation) |
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Error Table 7 |
Vie Sequence Pi-Bus Errors (All Modules) |
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Error Table 8 |
H0 Pi-Bus Errors (Slave Mode Operation) |
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Error Table 9 |
H1 Through HAn Pi-Bus Errors (Slave Mode Operation) |
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Error Table 10 |
D0 Through DAn Pi-Bus Errors (Slave Mode Operation) |
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Error Table 11 |
H0 Through HZ Errors (Master Mode) |
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Error Table 12 |
HA0 Through HAn Errors or HA0 Through HAn+2 for Parameter Writes (Master Mode) |
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Error Table 13 |
D0 Through DZ Errors (Master Mode) |
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Error Table 14 |
DA0 Through DAn+2 Errors (Master Mode) |
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Error Table 15 |
Nontransfer Cycles From HAn+3 Through H0 Errors, Parameter Write (Master Mode) |
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