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J1850 Compatible Node Development
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English
Abstract
Given the fact that multiplex bus architectures are gaining acceptance, the need arises for hardware capable of implementing the desired structure Off-the-shelf technology exists that can be utilized for the design and development of J1850 compatible nodes A systems engineering approach to the design of a J1850 compatible node is taken A genenc model of a network node is defined and the design of a simple node is described The results of a market survey of available hardware and design tools are presented. This information is then used to develop several design approaches which are described and evaluated.
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Citation
Riley, M. and Moyer, R., "J1850 Compatible Node Development," SAE Technical Paper 960125, 1996, https://doi.org/10.4271/960125.Also In
References
- Beyeler Bruce Langley Todd “Using the MC68332 TPU to Implement the J1850 Protocol” SAE paper 940137
- Harmon Joe Randel Rob Sferrazza Paul “Architecture and Operation of the HIP7030A2 8-Bit J1850 Microcontroller,” SAE paper 950034
- Malusardi Pietro “Use of One ST9 Timer for Handling a J1850 50 Kbit/Sec Implementation,” SAE paper 910710
- Sferrazza Paul Halter Rick Stark John “Architecture and Operation of the HIP7010 J1850 Byte-Level Interfere Circuit,” SAE paper 950035