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Architecture and Operation of the HIP7010 J1850 Byte-Level Interface Circuit
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Abstract
As a cost effective solution to making microcontroller based systems “J1850[1] aware”, a peripheral device (the HIP7010) was developed to extend the capabilities of standard microcontrollers. From the perspective of the Host, the peripheral device handles J1850 messages as a series of bytes (similar in concept to a universal asynchronous receiver/transmitter [UART]).
The architecture of the HIP7010 is discussed. The design of the J1850 interface, state machine, status/control blocks, cyclical redundancy check (CRC) hardware, host interface, and fail-safe features are detailed. Illustrations are provided of: Host/HIP7010 interfacing; message transmission and reception; error handling; and In-Frame Response (IFR) generation.
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Authors
Citation
Sferrazza, P., Halter, R., and Stark, J., "Architecture and Operation of the HIP7010 J1850 Byte-Level Interface Circuit," SAE Technical Paper 950035, 1995, https://doi.org/10.4271/950035.Also In
References
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- HIP7020 Technical Specification 1994 Harris Semiconductor Melbourne, FL.
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- HIP7010 Technical Specification 1994 Harris Semiconductor Melbourne, FL.
- Harmon, Randel Sferrazza Architecture and Operation of the HIP7030A2 8-Bit J1850 Controller 1995 SAE Paper 950034 SAE International Warrendale, PA.