This content is not included in
your SAE MOBILUS subscription, or you are not logged in.
Predicting MEMS Package Level Failure Modes in Automotive Applications
Technical Paper
2016-01-0266
ISSN: 0148-7191, e-ISSN: 2688-3627
Annotation ability available
Sector:
Language:
English
Abstract
The use of Micro Electro-Mechanical Systems (MEMS) for measuring accelerations, pressure, gyroscopic yaw rate and humidity in engine controls, inflatable restraint, braking, stability and other safety critical vehicle systems is increasing. Their use in these safety critical systems in high stress automotive environments makes ensuring their reliability and durability essential tasks, especially as the Vehicle System Functional Safety requirements of ISO-26262 are being implemented across the industry. A Design for Reliability (DfR) approach that applies Physics of Failure methods to evaluate and eliminate or mitigate susceptibilities to failure modes of a device during the design of a product is the most effective and efficient way to achieve Functional Safety levels of reliability-durability.
MEMS packages exhibit several failure modes that can be predicted as a device is designed using modern Computer Aided Engineering (CAE) software tools. This paper provides a methodology for using the Sherlock ADA CAE APP to rapidly create a high-fidelity model of a MEMS interposer with all the conductor geometries. The two failure modes that are explored with this model are:
- Package warpage due to copper imbalance between the two sides of the MEMS interposer. If a Coefficient of Thermal Expansion (CTE) mismatch due to copper imbalance exists between the two sides, bending of the package can occur to such a degree that it becomes impossible to assemble the solder interconnects.
- Filled microvia delamination that can occur when the filled microvias have copper structures that can delaminate from the copper traces in the conductor layers.
High-fidelity CAE modeling where each layer can be meshed based on the actual geometry of the layout of a MEMS device provides a predictive tool that allows designers to optimize the design to balance the layout without the need for costly and time consuming manufacture and testing of prototype parts.
Recommended Content
Technical Paper | Holistic Model-Based Development Process |
Technical Paper | Model-Driven Code Generation and Analysis |
Technical Paper | Static, Dynamic and Optimization CAE Evaluation Applied on Vehicle Jack Support |
Authors
Topic
Citation
Caswell, G. and McLeish, J., "Predicting MEMS Package Level Failure Modes in Automotive Applications," SAE Technical Paper 2016-01-0266, 2016, https://doi.org/10.4271/2016-01-0266.Also In
References
- Shukla , R. , Murali V. , and Bhansali A. Flip chip CPU package technology at Intel: a technology and manufacturing overview Electronic Components and Technology Conference, 1999 Proceedings. 49th. IEEE
- McLeish , J. and Haeberle , R. Moving Automotive Electronics from Reliability/Durability Testing to Virtual Validation Modeling Using a Physics of Failure CAE App SAE Int. J. Passeng. Cars - Electron. Electr. Syst. 7 2 369 376 2014 10.4271/2014-01-0233
- Li , Yuan Accurate predictions of flip chip BGA warpage Electronic Components and Technology Conference. IEEE; 1999 2003
- Wang , Jianjun et al. Creep behavior of a flip-chip package by both FEM modeling and real time Moiré interferometry Journal of Electronic Packaging 120 2 1998 179 185
- Ning , Yan , Azarian Michael H. , and Pecht Michael Influence of Plating Quality on Reliability of Microvias IPC APEX Expo 2015
- Reid , Paul Reid on Reliability: Microvia Robustness and Corner Cracks ICONNECT007 June 27, 2012
- Ryu Suk-Kyu , Lu Kuan-Hsun , Im Jay , Huang Rui and Ho Paul S. Stress-Induced Delamination Of Through Silicon Via Structures AIP Conf. Proc. 1378 153 2011 10.1063/1.3615702
- Wang Ming-Han , Wu Mei-Ling Thermo-mechanical Stress of Underfilled 3D IC Packaging IEEE EuroSimE 7-9April, 2014
- Myers , Alan M. et al. Via Hole Profile and Method of Fabrication U.S. Patent No. 5,470,790 28 Nov. 1995
- Yeoh , Hwai Peng et al. Flip chip pin grid array (fc-pga) packaging technology Electronics Packaging Technology Conference, 2000.(EPTC 2000). Proceedings of 3rd. IEEE 2000
- Gurrum , Siva Mechanical Modeling Advances Improve Semiconductor Packaging Electronic Design Jun 3 2014