This content is not included in your SAE MOBILUS subscription, or you are not logged in.

A Flexible High-Performance Accelerator Platform for Automotive Sensor Applications

Journal Article
2012-01-0939
ISSN: 1946-4614, e-ISSN: 1946-4622
Published April 16, 2012 by SAE International in United States
A Flexible High-Performance Accelerator Platform for Automotive Sensor Applications
Sector:
Citation: Sahlbach, H., Whitty, S., and Ernst, R., "A Flexible High-Performance Accelerator Platform for Automotive Sensor Applications," SAE Int. J. Passeng. Cars - Electron. Electr. Syst. 5(1):280-291, 2012, https://doi.org/10.4271/2012-01-0939.
Language: English

References

  1. Ahn, J.H. Dally, W.J. Khailany, B. Kapasi, U.J. Das, A. “Evaluating the Imagine Stream Architecture” SIGARCH Comput. Archit. News 32 2 14 2004
  2. Anthony, R. Rettberg, A. Chen, D. Jahnich, I. de Boer, G. Ekelin, C. “Towards a Dynamically Reconfigurable Automotive Control System Architecture” Embedded System Design: Topics, Techniques and Trends Springer Boston 2007
  3. Automated Imaging Association “Specifications of the Camera Link Interface Standard for Digital Cameras and Frame Grabbers, Version 1.1” Technical report Automated Imaging Association 2004
  4. AUTOSAR GbR “AUTOSAR - Technical Overview V2.2.1” Technical report AUTOSAR GbR 2008
  5. Becker, J. Huebner, M. Hettich, G. Constapel, R. Eisenmann, J. Luka, J. “Dynamic and Partial FPGA Exploitation” Proceedings of the IEEE 95 438 452 2007
  6. Blythe, D. “Rise of the Graphics Processor” Proceedings of IEEE 96 5 761 778 May 2008
  7. Claus, C. Stechele, W. Herkersdorf, A. “Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems” Information Technology 49 181 187 2007
  8. DaVinci Homepage 2008
  9. Dutta, S. Jensen, R. Rieckmann, A. “Viper: A multiprocessor SoC for advanced set-top box and digital TV systems” IEEE Design and Test of Computers, Sip 21 31 Oct 2001
  10. Heithecker, S. Lucas, A. Ernst, R. “A high-end real-time digital film processing reconfigurable platform” EURASIP J. Embedded Syst. 2007
  11. HiTech Global “Xilinx Virtex-5 LX330T, FX200T, SX240T PCI Express (Gen 1 & Gen 2), PPC 440, DSP, & RocketIO GTP/GTX Platform” http://www.hitechglobal.com/Boards/PCIExpressLX330T.htm 2010
  12. Horn, B.K.P. Schunck, B.G. “Determining Optical Flow” Artificial Intelligence 17 185 203 1981
  13. Jai, “CV-M4+/ M4+CL, CV-M7+/M7+CL Operation Manual” 2010
  14. Lee, E.A. Messerschmitt, D.G. “Synchronous Data Flow” Proceedings of the IEEE 75 1235 1245 September 1987
  15. Katz, D. Lukasiak, T. Gentile, R. “Use of Video Technology To Improve Automotive Safety Becomes More Feasible with Blackfin Processors” Technical report, Analog Devices 2004
  16. Kopetz, H. Ademaj, A. Grillinger, P. Steinhammer, K. “The time-triggered Ethernet (TTE) design” Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC) 2005
  17. Kyo, S. Okazaki, S. “In-vehicle vision processors for driver assistance systems” ASP-DAC ′08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference 2008
  18. Lucas, A. Heithecker, S. Ernst, R. “FlexWAFE - a high-end real-time stream processing library for FPGAs” Proceedings of the 44th annual Design Automation Conference (DAC ′07) 916 921 2007
  19. Lucas, A. Sahlbach, H. Whitty, S. Heithecker, S. Ernst, R. “Application development with the FlexWAFE real-time stream processing architecture for FPGAs” ACM Trans. Embed. Comput. Syst. 9 1 2009
  20. Lucas, B.D. Kanade, T. “An iterative image registration technique with an application to stereo vision” Proceedings of Imaging Understanding Workshop 1981
  21. Obermaisser, R. El Salloum, C. Huber, B. Kopetz, H. “From a federated to an integrated automotive architecture” IEEE Transactions on Computer-Aided Design of Integrated Ciruits and Systems 28 956 965 2009
  22. Osterloh, B. Michalik, H. Fiethe, B. Bubenhagen, F. “Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS) 2007
  23. Sahlbach, H. Whitty, S. Bende, O. Ernst, R. “A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture” International Conference on Field Programmable Logic and Applications 2010
  24. Sanz, C. Garrido, M.J. Meneses, J.M. “VLSI Architecture for Motion Estimation using the Block-Matching Algorithm” EDTC 310 1996
  25. Sony Global “Sony Gigabit Video Interface (GVIF) Product Info” http://www.sony.net/Products/SCHP/application/gvif/product/index.html 2011
  26. Spiteri, T. Vafiadis, G. Nunez-Yanez, J.L. “A toolset for the analysis and optimization of motion estimation algorithms and processors” Proc. of Int. Conf. on Field Programmable Logic and Applications (FPL) 2009
  27. Stein, G.P. Rushinek, E. Hayun, G. Shashua, A. “A Computer Vision System on a Chip: a case study from the automotive domain” Proceedings of IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPRW) 2005
  28. Tapp, S. “XAPP973: Indirect Programming of BPI PROMs with Virtex-5 FPGAs” Technical report Xilinx Inc. 2010
  29. Thrun, S. “Winning the DARPA Grand Challenge” Machine, Learning: ECML 2006 , volume 4212 of Lecture Notes in Computer Science 4 4 Springer Berlin / Heidelberg 2006
  30. Thomson, “Scream 4K/2K Resolution-Independent Grain Reducer” 2008
  31. Voigtländer, P. “ADTF: Framework for Driver Assistance and Safety Systems” ATZ 2008 09 2008
  32. Whitty, S. Sahlbach, H. Hurlburt, B. Ernst, R. Putzke-Röming, W. “Application-specific memory performance of a heterogeneous reconfigurable architecture” Proc. of Design, Automation and Test in Europe (DATE ′10) 387 392 2010
  33. Xilinx Inc “DS643: Multi-Port Memory Controller Product Specification” 2010
  34. Xilinx Inc “UG191: Virtex-5 FPGA Configuration User Guide” 2010
  35. Yap, S.Y. McCanny, J. “A VLSI architecture for variable block size video motion estimation” IEEE Transactions on Circuits and Systems 51 7 384 389 July 2004
  36. Yasuda, M. Watanabe, M. “Dynamically reconfigurable vision-chip architecture” Proc. of Int. Conf. on Field Programmable Logic and Applications (FPL) 2010

Cited By