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Artificial Intelligence-Based Field-Programmable Gate Array Accelerator for Electric Vehicles Battery Management System

Journal Article
12-07-03-0016
ISSN: 2574-0741, e-ISSN: 2574-075X
Published January 04, 2024 by SAE International in United States
Artificial Intelligence-Based Field-Programmable Gate Array
                    Accelerator for Electric Vehicles Battery Management System
Sector:
Citation: Nagarale, S. and Patil , B., "Artificial Intelligence-Based Field-Programmable Gate Array Accelerator for Electric Vehicles Battery Management System," SAE Intl. J CAV 7(3):2024, https://doi.org/10.4271/12-07-03-0016.
Language: English

Abstract:

The swift progress of electric vehicles (EVs) and hybrid electric vehicles (HEVs) has driven advancements in battery management systems (BMS). However, optimizing the algorithms that drive these systems remains a challenge. Recent breakthroughs in data science, particularly in deep learning networks, have introduced the long–short-term memory (LSTM) network as a solution for sequence problems. While graphics processing units (GPUs) and application-specific integrated circuits (ASICs) have been used to improve performance in AI-based applications, field-programmable gate arrays (FPGAs) have gained popularity due to their low power consumption and high-speed acceleration, making them ideal for artificial intelligence (AI) implementation. One of the critical components of EVs and HEVs is the BMS, which performs operations to optimize the use of energy stored in lithium-ion batteries (LiBs). Due to the nonlinear electrochemical nature of these batteries, estimating states of charge (SoC), states of health (SoH), and remaining useful life (RUL) is challenging. This article proposes an advanced AI-based BMS that uses LSTM to accurately estimate LiB states, providing crucial information for battery performance optimization. The proposed design is implemented in Python for training and validation. The hardware prototype is synthesized using Xilinx Vitis High-Level Synthesis (HLS) and implemented on Xilinx Zynq System-on-Chip (SoC) PYNQ Z2 board, achieving low root mean squared error (RMSE) values of 0.3438 and 0.3681 in training and validation, respectively.